US 12,439,640 B2
Reduced contact resistivity with PMOS germanium and silicon doped with boron gate all around transistors
Cory Bomberger, Portland, OR (US); Anand S. Murthy, Portland, OR (US); Rushabh Shah, Hillsboro, OR (US); Kevin Cook, Portland, OR (US); and Anupama Bowonder, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 25, 2021, as Appl. No. 17/359,422.
Prior Publication US 2022/0416043 A1, Dec. 29, 2022
Int. Cl. H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01)
CPC H10D 30/6735 (2025.01) [H10D 30/6729 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 62/151 (2025.01)] 12 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a plurality of nanowires above a sub-fin;
a gate stack over the plurality of nanowires and the sub-fin; and
epitaxial source or drain structures on opposite ends of the plurality of nanowires, the epitaxial source or drain structures comprising germanium and boron, and a protective layer comprising germanium, silicon and boron that at least partially covers the epitaxial source or drain structures, wherein the protective layer is approximately 3-15 nm in thickness when an atomic percentage of the germanium comprising the protective layer is approximately 45-55% to protect the epitaxial source or drain structures from being etched during fabrication processing and to provide low contact resistivity.