US 12,439,638 B2
FET with wrap-around silicide and fabrication methods thereof
Pei-Hsun Wang, Kaohsiung (TW); Chih-Chao Chou, Hsinchu (TW); Shih-Cheng Chen, New Taipei (TW); Jung-Hung Chang, Changhua County (TW); Jui-Chien Huang, Hsinchu (TW); Chun-Hsiung Lin, Hsinchu County (TW); and Chih-Hao Wang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on May 24, 2024, as Appl. No. 18/673,596.
Application 17/193,732 is a division of application No. 16/582,547, filed on Sep. 25, 2019, granted, now 10,944,009, issued on Mar. 9, 2021.
Application 18/673,596 is a continuation of application No. 18/066,141, filed on Dec. 14, 2022, granted, now 11,996,483.
Application 18/066,141 is a continuation of application No. 17/193,732, filed on Mar. 5, 2021, granted, now 11,695,076, issued on Jul. 4, 2023.
Claims priority of provisional application 62/753,466, filed on Oct. 31, 2018.
Prior Publication US 2024/0313118 A1, Sep. 19, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 30/67 (2025.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H10D 30/01 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/62 (2025.01)
CPC H10D 30/6713 (2025.01) [H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/28518 (2013.01); H10D 30/031 (2025.01); H10D 30/6735 (2025.01); H10D 30/6741 (2025.01); H10D 30/6757 (2025.01); H10D 62/116 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 64/62 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor fin protruding from a substrate;
an isolation structure surrounding sidewalls of the semiconductor fin;
a gate structure extending over a channel region of the semiconductor fin;
a source/drain (S/D) feature extending from an S/D region of the semiconductor fin, wherein the S/D feature is disposed adjacent the gate structure, and an extended portion of the S/D feature extends over the isolation structure; and
a silicide feature disposed on the extended portion of the S/D feature, wherein a portion of the silicide feature is disposed laterally between a sidewall of the gate structure and a sidewall of the S/D feature.