US 12,439,637 B2
Transistors, array of transistors, and array of memory cells individually comprising a transistor
Kamal M. Karda, Boise, ID (US); Haitao Liu, Boise, ID (US); and Sameer Chhajed, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 15, 2022, as Appl. No. 17/695,634.
Claims priority of provisional application 63/293,993, filed on Dec. 27, 2021.
Prior Publication US 2023/0207699 A1, Jun. 29, 2023
Int. Cl. H01L 29/786 (2006.01); H10B 12/00 (2023.01); H10D 30/67 (2025.01)
CPC H10D 30/6713 (2025.01) [H10B 12/31 (2023.02); H10D 30/6728 (2025.01)] 34 Claims
OG exemplary drawing
 
1. A transistor comprising:
a pair of source/drain regions having a channel region there-between;
a gate adjacent the channel region with a gate insulator being between the gate and the channel region, the gate having an external surface that is not between the gate and the channel region;
a fixed-charge material that is along the external surface of the gate and that is adjacent the source/drain regions; and
insulating material between the fixed-charge material and the source/drain regions, the insulating material and the fixed-charge material comprising different compositions relative one another, the fixed-charge material having charge density of at least 1×1011 charges/cm2.