US 12,439,635 B2
Vertical field effect transistor and method for the formation thereof
Jens Baringhaus, Sindelfingen (DE); Daniel Krebs, Aufhausen (DE); and Dick Scholten, Stuttgart (DE)
Assigned to ROBERT BOSCH GMBH, Stuttgart (DE)
Appl. No. 17/767,282
Filed by Robert Bosch GmbH, Stuttgart (DE)
PCT Filed Sep. 24, 2020, PCT No. PCT/EP2020/076738
§ 371(c)(1), (2) Date Apr. 7, 2022,
PCT Pub. No. WO2021/089230, PCT Pub. Date May 14, 2021.
Claims priority of application No. 10 2019 217 081.1 (DE), filed on Nov. 6, 2019.
Prior Publication US 2022/0367713 A1, Nov. 17, 2022
Int. Cl. H10D 30/63 (2025.01); H10D 12/01 (2025.01); H10D 30/01 (2025.01); H10D 62/10 (2025.01); H10D 62/832 (2025.01); H10D 62/85 (2025.01)
CPC H10D 30/635 (2025.01) [H10D 12/031 (2025.01); H10D 30/021 (2025.01); H10D 30/025 (2025.01); H10D 62/109 (2025.01); H10D 62/8325 (2025.01); H10D 62/8503 (2025.01)] 10 Claims
OG exemplary drawing
 
1. A vertical field effect transistor, comprising:
a drift area;
a semiconductor structure on or above the drift area;
a connection area on or above the semiconductor structure; and
a gate electrode, which is formed adjacent to at least one side wall of the semiconductor structure; and
a shielding structure, which is formed laterally adjacent to the connection area,
wherein the semiconductor structure has a lateral extension in a first section situated laterally adjacent to the gate electrode, in a second section contacting the drift area, and in a third section contacting the connection area, the lateral extension in the first section is less than the lateral extension in the second section, and/or less than the lateral extension in the first section.