US 12,439,634 B2
Semiconductor device
Shuhei Mitani, Kyoto (JP); Yuki Nakano, Kyoto (JP); Heiji Watanabe, Osaka (JP); Takayoshi Shimura, Osaka (JP); Takuji Hosoi, Osaka (JP); and Takashi Kirino, Osaka (JP)
Assigned to ROHM CO., LTD., Kyoto (JP)
Filed by ROHM CO., LTD., Kyoto (JP)
Filed on Aug. 24, 2023, as Appl. No. 18/454,820.
Application 18/454,820 is a continuation of application No. 17/680,864, filed on Feb. 25, 2022, granted, now 11,777,030.
Application 17/680,864 is a continuation of application No. 17/464,303, filed on Sep. 1, 2021, granted, now 11,296,223, issued on Apr. 5, 2022.
Application 17/464,303 is a continuation of application No. 17/328,822, filed on May 24, 2021, granted, now 11,610,992, issued on Mar. 21, 2023.
Application 17/328,822 is a continuation of application No. 17/016,989, filed on Sep. 10, 2020, granted, now 11,043,589, issued on Jun. 22, 2021.
Application 17/016,989 is a continuation of application No. 16/714,038, filed on Dec. 13, 2019, granted, now 10,804,392, issued on Oct. 13, 2020.
Application 16/714,038 is a continuation of application No. 16/418,360, filed on May 21, 2019, granted, now 10,546,954, issued on Jan. 28, 2020.
Application 16/418,360 is a continuation of application No. 15/868,389, filed on Jan. 11, 2018, granted, now 10,319,853, issued on Jun. 11, 2019.
Application 15/868,389 is a continuation of application No. 15/273,230, filed on Sep. 22, 2016, granted, now 9,893,180, issued on Feb. 13, 2018.
Application 15/273,230 is a continuation of application No. 14/995,454, filed on Jan. 14, 2016, granted, now 9,496,393, issued on Nov. 15, 2016.
Application 14/995,454 is a continuation of application No. 14/601,345, filed on Jan. 21, 2015, granted, now 9,257,521, issued on Feb. 9, 2016.
Application 14/601,345 is a continuation of application No. 14/148,766, filed on Jan. 7, 2014, granted, now 8,969,877, issued on Mar. 3, 2015.
Application 14/148,766 is a continuation of application No. 13/394,549, granted, now 8,653,533, issued on Feb. 18, 2014, previously published as PCT/JP2010/065057, filed on Sep. 2, 2010.
Claims priority of application No. 2009-206372 (JP), filed on Sep. 7, 2009; application No. 2009-206373 (JP), filed on Sep. 7, 2009; and application No. 2009-206374 (JP), filed on Sep. 7, 2009.
Prior Publication US 2023/0395713 A1, Dec. 7, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/04 (2006.01); H10D 30/60 (2025.01); H10D 30/63 (2025.01); H10D 30/66 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01); H10D 62/832 (2025.01); H10D 64/23 (2025.01); H10D 64/27 (2025.01); H10D 64/68 (2025.01); H10D 84/03 (2025.01); H10D 64/62 (2025.01)
CPC H10D 30/63 (2025.01) [H01L 21/02164 (2013.01); H01L 21/02178 (2013.01); H01L 21/0223 (2013.01); H01L 21/02236 (2013.01); H01L 21/02247 (2013.01); H01L 21/0445 (2013.01); H01L 21/049 (2013.01); H10D 30/60 (2025.01); H10D 30/66 (2025.01); H10D 30/668 (2025.01); H10D 62/151 (2025.01); H10D 62/378 (2025.01); H10D 62/8325 (2025.01); H10D 64/256 (2025.01); H10D 64/512 (2025.01); H10D 64/513 (2025.01); H10D 64/516 (2025.01); H10D 64/681 (2025.01); H10D 64/685 (2025.01); H10D 64/693 (2025.01); H10D 84/035 (2025.01); H01L 21/02252 (2013.01); H01L 21/02255 (2013.01); H10D 62/153 (2025.01); H10D 62/155 (2025.01); H10D 64/62 (2025.01)] 18 Claims
OG exemplary drawing
 
1. A SiC semiconductor device, comprising:
a semiconductor layer;
a well region of a second conductivity type formed on a surface layer portion of the semiconductor layer and that has a channel region defined therein;
a source region of a first conductivity type formed on a surface layer portion of the well region;
a gate insulating film formed on the semiconductor layer and located on the channel region and at least part of the source region; and
a gate electrode formed on the gate insulating film and opposed to the channel region of the well region where a channel is formed through the gate insulating film,
wherein the source region includes a portion that is lower by one stage than an upper surface of the well region, the channel region is formed as a straight line approximately, and the gate insulating film is formed on at least part of the portion that is lower by one stage.