US 12,439,632 B2
Memory arrays with vertical transistors and the formation thereof
Fatma Arzum Simsek-Ege, Boise, ID (US); Steve V. Cole, Boise, ID (US); Scott J. Derner, Boise, ID (US); and Toby D. Robbs, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 4, 2022, as Appl. No. 17/568,133.
Application 17/568,133 is a division of application No. 16/522,390, filed on Jul. 25, 2019, granted, now 11,222,975.
Prior Publication US 2022/0131003 A1, Apr. 28, 2022
Int. Cl. H10D 30/63 (2025.01); G11C 11/22 (2006.01); G11C 11/4091 (2006.01); H10B 12/00 (2023.01); H10B 51/10 (2023.01); H10D 30/01 (2025.01)
CPC H10D 30/63 (2025.01) [G11C 11/223 (2013.01); G11C 11/4091 (2013.01); H10B 12/03 (2023.02); H10B 12/053 (2023.02); H10B 12/34 (2023.02); H10B 12/48 (2023.02); H10B 51/10 (2023.02); H10D 30/025 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory cell coupled to a first digit line at a first level;
a second digit line at a second level coupled to a main sense amplifier;
a charge sharing device at a third level between the first and second levels and coupled to the first digit line and to a connector;
a vertical transistor at the third level and coupled between the first digit line and the connector; and
a contact coupled between the connector and the second digit line.