US 12,439,631 B2
Non-self-aligned wrap-around contact in a tight gate pitched transistor
Chanro Park, Clifton Park, NY (US); Ruilong Xie, Niskayuna, NY (US); Kangguo Cheng, Schenectady, NY (US); and Juntao Li, Cohoes, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Nov. 22, 2021, as Appl. No. 17/531,966.
Prior Publication US 2023/0163180 A1, May 25, 2023
Int. Cl. H10D 30/62 (2025.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01)
CPC H10D 30/6219 (2025.01) [H10D 30/024 (2025.01); H10D 30/031 (2025.01); H10D 30/6211 (2025.01); H10D 30/6713 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 62/151 (2025.01); H10D 64/01 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) comprising:
a substrate comprising first and second channels;
a shared source or drain (S/D) region between the first and second channels, the shared source or drain region comprising an uppermost surface and further comprising a second surface recessed from the uppermost surface and sidewalls extending from the uppermost surface to the second surface to define a recess;
first and second gate structures comprising gate metal disposed on the first and second channels; and
an S/D wrap-around contact (WAC), which comprises a first portion which extends into the recess to contact the second surface and the sidewalls and which is wrapped around the S/D region at an exterior of the recess,
wherein the S/D region comprises epitaxy having a negatively profiled section, the S/D WAC forms an elongate void under the negatively profiled section of the epitaxy of the S/D region and the negatively profiled section and the longest dimension of the elongate void are correspondingly angled relative to the substrate.