| CPC H10D 30/475 (2025.01) [H10D 62/8503 (2025.01); H10D 84/01 (2025.01); H10D 84/84 (2025.01)] | 18 Claims |
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2. A semiconductor device, comprising:
a first transistor with a first gate terminal, a first source terminal, and a first drain terminal, the first transistor being a depletion mode transistor and including a plurality of two-dimensional carrier channels of a conductivity type being one of a n-type or a p-type conductivity;
a second transistor with a second gate terminal, a second source terminal, and a second drain terminal, the second transistor being an enhancement mode transistor;
a gate-source interconnect forming an electrical connection between the first gate terminal and the second source terminal;
a substrate; and
a buffer layer disposed over the substrate, wherein the first transistor and the second transistor are disposed over the buffer layer; and
a drain-source interconnect forming an electrical connection between the first source terminal and the second drain terminal, wherein:
the drain-source interconnect includes an ohmic contact that makes contact with the plurality of two-dimensional carrier channels; or
the drain-source interconnect includes a doped semiconductor sidewall, and wherein the plurality of two-dimensional carrier channels terminate at the doped semiconductor sidewall; or
the drain-source interconnect includes a heterostructure, and wherein the plurality of two-dimensional carrier channels terminate at the heterostructure.
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