US 12,439,627 B2
Gate structures to enable lower subthreshold slope in gallium nitride-based transistors
Sanyam Bajaj, Hillsboro, OR (US); Michael S. Beumer, Portland, OR (US); Robert Ehlert, Portland, OR (US); Gregory P. McNerney, Beaverton, OR (US); Nicholas Minutillo, Beaverton, OR (US); Xiaoye Qin, Beaverton, OR (US); Johann C. Rode, Hillsboro, OR (US); Atsunori Tanaka, Hillsboro, OR (US); Suresh Vishwanath, Portland, OR (US); and Patrick M. Wallace, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 21, 2021, as Appl. No. 17/557,827.
Prior Publication US 2023/0197840 A1, Jun. 22, 2023
Int. Cl. H10D 30/47 (2025.01); H10D 30/01 (2025.01); H10D 62/824 (2025.01); H10D 62/85 (2025.01); H10D 64/27 (2025.01)
CPC H10D 30/4738 (2025.01) [H10D 30/015 (2025.01); H10D 62/824 (2025.01); H10D 62/8503 (2025.01); H10D 64/411 (2025.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a substrate;
a buffer layer on the substrate, the buffer layer comprising a first group III-nitride (III-N) material;
a channel layer on the buffer layer, the channel layer comprising a second III-N material;
one or more polarization layers on the channel layer, the one or more polarization layers comprising a third III-N material comprising a first group III constituent and a second group III constituent;
a plurality of p-type doped layers on the one or more polarization layers, each of the plurality of p-type doped layers comprising a first p-type dopant and the third III-N material, wherein each successive layer of the first p-type doped layers has a lower proportion of the first group III constituent to the second group III constituent relative to a layer below it;
a p-type doped layer on the plurality of p-type doped layers comprising a second p-type dopant and a fourth III-N material; and
a source region adjacent one end of the channel layer; and
a drain region adjacent another end of the channel layer.