US 12,439,626 B2
Self-aligned memory architecture comprising a memory array associated with pillars and polysilicon material
John Hopkins, Meridian, ID (US); and Jordan D. Greenlee, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 1, 2022, as Appl. No. 17/804,997.
Prior Publication US 2023/0395704 A1, Dec. 7, 2023
Int. Cl. H10D 30/01 (2025.01); H10B 43/35 (2023.01); H10D 30/69 (2025.01)
CPC H10D 30/0413 (2025.01) [H10B 43/35 (2023.02); H10D 30/69 (2025.01)] 7 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a substrate;
a stack of alternating materials positioned above the substrate, the stack of alternating materials comprising dielectric materials and conductive materials, the conductive materials each comprising a word line for a memory cell of a plurality of memory cells associated with the stack of alternating materials;
a pillar positioned above the substrate and extending through the stack of alternating materials, wherein the stack of alternating materials and the pillar form the plurality of memory cells;
a polysilicon material above the pillar and associated with a selector gate for the plurality of memory cells, the polysilicon material extending away from the pillar and through the stack of alternating materials, wherein the polysilicon material terminates before a top surface of the stack of alternating materials that is opposite the substrate; and
a nitride material above the polysilicon material and coupled with the stack of alternating materials below the top surface of the stack of alternating materials, the nitride material aligned with the polysilicon material.