| CPC H10D 30/024 (2025.01) [H10D 30/6211 (2025.01); H10D 30/6219 (2025.01); H10D 84/013 (2025.01); H10D 84/038 (2025.01)] | 20 Claims |
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1. A method of forming a semiconductor device structure, the method comprising:
forming a gate structure over a substrate;
forming an epitaxial source/drain region adjacent to the gate structure;
forming a dielectric layer over the epitaxial source/drain region, the dielectric layer comprising an opening exposing sidewalls of the dielectric layer and a top surface of the epitaxial source/drain region;
forming a silicide layer on the epitaxial source/drain region;
selectively forming a metal capping layer on and interfacing the silicide layer by a first deposition process, wherein the metal capping layer comprises tungsten, molybdenum, or a combination thereof; and
filling the opening with a first conductive material by a second deposition process different from the first deposition process, wherein the first conductive material fills the opening in a bottom-up manner from the metal capping layer.
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