US 12,439,622 B2
Semiconductor device and manufacturing method of semiconductor device
Kaname Mitsuzuka, Matsumoto (JP); and Tohru Shirakawa, Matsumoto (JP)
Assigned to FUJI ELECTRIC CO., LTD., Kanagawa (JP)
Filed by FUJI ELECTRIC CO., LTD., Kawasaki (JP)
Filed on Dec. 20, 2022, as Appl. No. 18/069,203.
Claims priority of application No. 2022-015236 (JP), filed on Feb. 2, 2022.
Prior Publication US 2023/0246097 A1, Aug. 3, 2023
Int. Cl. H10D 12/00 (2025.01); H01L 21/265 (2006.01); H10D 12/01 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01); H10D 64/23 (2025.01)
CPC H10D 12/491 (2025.01) [H01L 21/26506 (2013.01); H10D 12/038 (2025.01); H10D 62/133 (2025.01); H10D 62/393 (2025.01); H10D 64/231 (2025.01)] 23 Claims
OG exemplary drawing
 
1. A semiconductor device comprising a gate trench portion and a first trench portion adjacent to the gate trench portion, the semiconductor device comprising:
a drift region of a first conductivity type, which is provided in a semiconductor substrate;
a base region of a second conductivity type, which is provided above the drift region;
an emitter region of the first conductivity type, which is provided above the base region and has a doping concentration higher than a doping concentration of the drift region; and
a contact region of the second conductivity type, which is provided above the base region and has a doping concentration higher than a doping concentration of the base region,
wherein the contact region includes a first contact portion provided on a front surface of the semiconductor substrate, and a second contact portion which has a doping concentration different from a doping concentration of the first contact portion and is provided alternately with the first contact portion in a trench extending direction on a side wall of the first trench portion.