| CPC H10D 8/605 (2025.01) [H10D 8/051 (2025.01); H10D 30/668 (2025.01); H10D 62/106 (2025.01)] | 9 Claims |
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1. A power semiconductor device comprising:
a silicon substrate having a first surface, and a second surface that is opposite the first surface and has a first portion and a second portion, the silicon substrate including
a first semiconductor region that has a first conductivity type,
a second semiconductor region that has a second conductivity type different from the first conductivity type,
a third semiconductor region that has the first conductivity type, and is separated from the first semiconductor region by the second semiconductor region, and
a fourth semiconductor region that has the second conductivity type, and is separated from the second semiconductor region by the third semiconductor region;
a gate insulating film that extends between the first semiconductor region and the third semiconductor region, and faces the second semiconductor region;
a gate electrode that faces the second semiconductor region with the gate insulating film interposed between the gate electrode and the second semiconductor region;
a first electrode that is provided on the first surface of the silicon substrate, and is in contact with the third semiconductor region and the fourth semiconductor region;
a barrier metal layer provided on the first portion of the second surface of the silicon substrate;
a second electrode provided on the second surface of the silicon substrate, and separated from the first portion of the second surface of the silicon substrate by the barrier metal layer, the second electrode including
an Al—Si layer in contact with the second portion of the second surface of the silicon substrate, and
an Al layer separated from the second portion of the second surface of the silicon substrate by the Al—Si layer; and
a polycrystalline silicon layer that is in contact with the second electrode, away from the second surface of the silicon substrate.
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