| CPC H10D 1/692 (2025.01) [H01L 21/4857 (2013.01); H01L 23/49816 (2013.01); H01L 23/49894 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); H01L 2224/16235 (2013.01)] | 23 Claims |

|
1. A microelectronic device package, comprising:
a chip comprising an integrated circuit (IC); and
a routing structure, wherein the routing structure comprises:
redistribution features interconnected to the chip through first-level interconnect features on a first side of the routing structure, wherein the redistribution features are of a first metal composition that is predominantly Cu, and terminate at interfaces on a second, opposite, side of the routing structure, that are to couple the package to second-level interconnect features; and
a first dielectric material between adjacent ones of the redistribution features, wherein the first dielectric material comprises a polymer; and
a metal-insulator-metal (MIM) capacitor structure between the first-level interconnect features and the interfaces, wherein the MIM capacitor structure comprises:
an electrode and a second electrode, both of a second metal composition, different than the first metal composition; and
an insulator between the electrode and the second electrode, wherein:
the insulator comprises a second dielectric material comprising silicon and at least one of oxygen or nitrogen;
the electrode is coupled to one of the first-level interconnect features through a first of the redistribution features; and
the second electrode is coupled through a second of the redistribution features to either a second of the first-level interconnect features, or a first of the interfaces.
|