US 12,439,615 B2
Semiconductor structure and method for forming same
Meng Huang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 29, 2022, as Appl. No. 17/936,846.
Application 17/936,846 is a continuation of application No. PCT/CN2022/105642, filed on Jul. 14, 2022.
Claims priority of application No. 202210729634.5 (CN), filed on Jun. 24, 2022.
Prior Publication US 2023/0014263 A1, Jan. 19, 2023
Int. Cl. H01L 49/02 (2006.01); H01L 21/308 (2006.01); H01L 21/762 (2006.01); H01L 27/108 (2006.01); H10B 12/00 (2023.01); H10D 1/00 (2025.01); H10D 1/68 (2025.01); H10D 30/67 (2025.01)
CPC H10D 1/042 (2025.01) [H01L 21/308 (2013.01); H01L 21/76224 (2013.01); H10B 12/00 (2023.02); H10D 1/716 (2025.01); H10D 30/6735 (2025.01)] 15 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor structure, comprising:
providing a semiconductor substrate, wherein stack structures and isolation structures alternately arranged along a first direction are formed on the semiconductor substrate, and each of the stack structures comprises first semiconductor layers and second semiconductor layers alternately stacked along a second direction;
forming a support structure in the stack structures and the isolation structures;
etching the stack structures and the isolation structures to form a plurality of zigzag first semiconductor pillars in an array arrangement along the first direction and the second direction, wherein an interspace is formed between the zigzag first semiconductor pillars, wherein the zigzag first semiconductor pillars are formed by:
forming a mask layer with a specific pattern on surfaces of the stack structures and the isolation structures, wherein the specific pattern comprises a plurality of sub-patterns arranged along a third direction in sequence, and the sub-patterns exposes part of each of the stack structures and part of each of the isolation structures; and
forming first concave structures by thinning each of the second semiconductor layers in each of the stack structures exposed by the sub-patterns; wherein an untreated part of each of the second semiconductor layers constitutes first convex structures; and a projection area of each of the first convex structures along the third direction is greater than a projection area of each of the first concave structures along the third direction;
each of the zigzag first semiconductor pillars comprises the first convex structures and the first concave structures alternately arranged along the third direction, and the zigzag first semiconductor pillars are supported by the support structure; the first direction, the second direction and the third direction are perpendicular to one another, and the second direction is perpendicular to a top surface of the semiconductor substrate; and
forming capacitor structures in the interspace.