US 12,439,613 B2
Manufacturing method memory device having laterally extending capacitors of different lengths and levels
Hsih-Yang Chiu, Taoyuan (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Jul. 1, 2022, as Appl. No. 17/856,458.
Prior Publication US 2024/0006471 A1, Jan. 4, 2024
Int. Cl. H10D 1/00 (2025.01); H10B 12/00 (2023.01); H10D 1/68 (2025.01)
CPC H10D 1/042 (2025.01) [H10B 12/0335 (2023.02); H10D 1/043 (2025.01); H10D 1/714 (2025.01); H10D 1/716 (2025.01)] 14 Claims
OG exemplary drawing
 
1. A method of manufacturing a memory device, comprising:
providing a semiconductor substrate;
disposing a first insulating layer over the semiconductor substrate;
disposing a first bottom electrode over the first insulating layer;
disposing a first dielectric layer over the first bottom electrode;
removing a portion of the first dielectric layer to form a first recess extending through the first dielectric layer;
disposing a first capacitor dielectric conformal to the first recess and over the first bottom electrode; and
forming a first top electrode within the first recess and surrounded by the first capacitor dielectric;
disposing a second insulating layer over the first top electrode and the first dielectric layer;
disposing a second bottom electrode over the second insulating layer;
disposing a second dielectric layer over the second bottom electrode;
removing a portion of the second dielectric layer to form a second recess extending through the second dielectric layer;
disposing a second capacitor dielectric conformal to the second recess and over the second bottom electrode; and
forming a second top electrode within the second recess and surrounded by the second capacitor dielectric,
wherein the second capacitor dielectric and the second top electrode extend laterally over the second bottom electrode and the semiconductor substrate;
wherein the first capacitor dielectric and the first top electrode extend laterally over the first bottom electrode and the semiconductor substrate.