US 12,439,612 B2
Semiconductor device and manufacturing method of the semiconductor device
Hyung Keun Kim, Icheon (KR); Jun Ku Ahn, Icheon (KR); Jun Young Lim, Icheon (KR); and Sung Lae Cho, Icheon (KR)
Assigned to SK hynix Inc., Icheon (KR)
Filed by SK hynix Inc., Icheon (KR)
Filed on Apr. 2, 2024, as Appl. No. 18/624,983.
Application 18/624,983 is a division of application No. 17/234,483, filed on Apr. 19, 2021, granted, now 11,974,442.
Claims priority of application No. 10-2020-0158217 (KR), filed on Nov. 23, 2020.
Prior Publication US 2024/0251571 A1, Jul. 25, 2024
Int. Cl. H10B 63/00 (2023.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 70/00 (2023.01)
CPC H10B 63/845 (2023.02) [H10B 61/00 (2023.02); H10N 50/01 (2023.02); H10N 70/023 (2023.02); H10N 70/823 (2023.02); H10B 61/10 (2023.02); H10B 63/24 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a stack structure including first electrodes and insulating layers alternately stacked on each other;
a second electrode passing through the stack structure; and
variable resistance patterns each interposed between the second electrode and a corresponding one of the first electrodes,
wherein the first electrodes include first sidewalls that each face the second electrode,
wherein the insulating layers include second sidewalls that each face the second electrode,
wherein at least a part of each of the variable resistance patterns protrudes farther towards the second electrode than a corresponding one of the second sidewalls, and
wherein the second electrode includes an air gap overlapping at least one of the variable resistance patterns.