US 12,439,611 B2
Memory cell and memory array select transistor
Jin-Woo Han, San Jose, CA (US); and Yuniarto Widjaja, Cupertino, CA (US)
Assigned to Zeno Semiconductor, Inc., Sunnyvale, CA (US)
Filed by Zeno Semiconductor, Inc., Sunnyvale, CA (US)
Filed on Jan. 16, 2024, as Appl. No. 18/414,135.
Application 18/414,135 is a continuation of application No. 18/171,497, filed on Feb. 20, 2023, granted, now 11,943,937.
Application 18/171,497 is a continuation of application No. 16/740,652, filed on Jan. 13, 2020, granted, now 11,600,663, issued on Mar. 7, 2023.
Claims priority of provisional application 62/933,880, filed on Nov. 11, 2019.
Claims priority of provisional application 62/817,484, filed on Mar. 12, 2019.
Prior Publication US 2024/0155848 A1, May 9, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 63/00 (2023.01); H10B 41/00 (2023.01); H10B 61/00 (2023.01)
CPC H10B 63/34 (2023.02) [H10B 41/00 (2023.02); H10B 61/22 (2023.02); H10B 63/32 (2023.02); H10B 63/84 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory array comprising:
a plurality of semiconductor devices configured to function as a memory select transistor with increased on-state drain current; wherein each of said semiconductor devices comprises:
a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type;
a buried layer having a second conductivity type selected from said p-type conductivity type and said n-type conductivity type and being different from said first conductivity type;
a body having said first conductivity type;
a source region and a drain region each having said second conductivity type and being separated by said body;
a gate positioned in between said source region and said drain region;
a charge trap layer containing a substantial number of charge trap centers that may absorb excess majority carrier, said charge trap layer contacting at least one of said source region and said drain region; and
an insulating layer comprising an STI contacting said charge trap layer;
wherein said semiconductor device is configured to function as a select transistor for at least one memory element connected to said drain region or said source region, wherein a state of said at least one memory element is determined by a resistivity of said at least one memory element.