| CPC H10B 63/24 (2023.02) [H10B 63/84 (2023.02)] | 20 Claims |

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1. A memory device comprising:
a plurality of first conductive lines on a substrate and extending in a first direction;
a plurality of second conductive lines on the plurality of first conductive lines and extending in a second direction intersecting the first direction; and
a plurality of memory cells respectively between the plurality of first conductive lines and the plurality of second conductive lines,
wherein each of the plurality of memory cells comprises a switching element and a variable resistance material layer, and
wherein the switching element comprises a material having a composition of [GeX PY SeZ](1-W) [O]W, where 0.15≤X≤0.50, 0.15≤Y≤0.50, 0.35≤Z≤0.70, and 0.01≤W≤0.10.
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