US 12,439,609 B2
Process technique for embedded memory
Chao-Yang Chen, Hefei (CN); Wen-Hsiung Chang, Hefei (CN); Zezhi Chen, Hefei (CN); and Zhichao Lu, San Jose, CA (US)
Assigned to HEFEI RELIANCE MEMORY LIMITED, Hefei (CN)
Filed by HEFEI RELIANCE MEMORY LIMITED, Hefei (CN)
Filed on Oct. 9, 2024, as Appl. No. 18/910,873.
Application 18/910,873 is a continuation of application No. PCT/CN2023/119564, filed on Sep. 19, 2023.
Prior Publication US 2025/0098178 A1, Mar. 20, 2025
Int. Cl. H10N 70/00 (2023.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01)
CPC H10B 63/22 (2023.02) [H10N 70/021 (2023.02); H10N 70/20 (2023.02); H10N 70/841 (2023.02)] 5 Claims
OG exemplary drawing
 
1. A method for manufacturing an integrated circuit comprising:
defining a memory region and a non-memory region on a semiconductor wafer;
depositing a first interlayer dielectric layer on a first bottom metal layer in the memory region and a second bottom metal layer in the non-memory region;
forming a first conductive structure in the memory region and a second conductive structure in the non-memory region by etching the first interlayer dielectric layer using a first photolithography process comprising a first photomask, wherein the first conductive structure is configured to be a first bottom electrode in the memory region;
depositing a memory stack layer in the memory region and the non-memory region;
forming a memory element in the memory region by etching the memory stack layer using a second photolithography process comprising a second photomask;
depositing a second interlayer dielectric layer in the memory region and the non-memory region; and
forming a first via in the memory region and a second via in the non-memory region by etching the second interlayer dielectric layer using a third photolithography process comprising a third photomask, wherein the first photomask and the third photomask comprise a same pattern.