US 12,439,608 B2
MRAM integration with self-aligned direct back side contact
Ruilong Xie, Niskayuna, NY (US); Nicholas Anthony Lanzillo, Wynantskill, NY (US); Koichi Motoyama, Clifton Park, NY (US); Brent A. Anderson, Jericho, VT (US); Michael Rizzolo, Delmar, NY (US); and Lawrence A. Clevenger, Saratoga Springs, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Aug. 9, 2022, as Appl. No. 17/884,002.
Prior Publication US 2024/0057345 A1, Feb. 15, 2024
Int. Cl. H10B 61/00 (2023.01); H10D 30/00 (2025.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01); H10N 59/00 (2023.01); H10B 63/00 (2023.01)
CPC H10B 61/22 (2023.02) [H10D 30/501 (2025.01); H10N 50/01 (2023.02); H10N 50/80 (2023.02); H10N 59/00 (2023.02); H10B 63/30 (2023.02); H10N 50/10 (2023.02)] 24 Claims
OG exemplary drawing
 
20. A semiconductor structure comprising:
a magnetoresistive random access memory (MRAM) device region comprising a MRAM comprising a first electrode, a MRAM stack, and a second electrode, and located in a back side of a wafer, a first transistor having a first source/drain structure located beneath the MRAM, and a first back side source/drain contact structure directly connecting the first electrode of the MRAM to a first source/drain structure of a first transistor, wherein the first back side source/drain contact structure has an outermost sidewall that is substantially vertically aligned to an outermost sidewall of both the first source/drain structure of the first transistor and the first electrode; and
a logic device region located adjacent to the MRAM device region, wherein the logic device region comprises a second transistor located in a front side of the wafer and having a first source/drain structure located on a first side of a functional gate structure of the second transistor, and a second back side source/drain contact structure directly connecting the first source/drain structure of the functional gate structure of second transistor to a back side power rail.