US 12,439,606 B1
Gate coupled non-linear polar material based capacitors for memory and logic
Noriyuki Sato, Hillsboro, OR (US); Tanay Gosavi, Portland, OR (US); Rafael Rios, Austin, TX (US); Amrita Mathuriya, Portland, OR (US); Niloy Mukherjee, San Ramon, CA (US); Mauricio Manfrini, Heverlee (BE); Rajeev Kumar Dokania, Beaverton, OR (US); Somilkumar J. Rathi, San Jose, CA (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Mar. 18, 2022, as Appl. No. 17/655,423.
Application 17/655,423 is a continuation of application No. 17/654,917, filed on Mar. 15, 2022, granted, now 12,324,163.
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 53/30 (2023.01); H10B 69/00 (2023.01)
CPC H10B 53/30 (2023.02) 18 Claims
OG exemplary drawing
 
1. A system comprising:
a first region comprising:
a transistor in a first level, the transistor comprising:
a source;
a drain;
a gate between the source and the drain;
a drain contact coupled with the drain; and
a gate contact coupled with the gate;
a memory coupled to the transistor, wherein the memory comprises: bit-cells, wherein one of the bit-cells comprises:
a first conductive interconnect within a first dielectric in a second level, wherein the first conductive interconnect is electrically coupled with the gate contact, and wherein the first conductive interconnect comprises a first lateral thickness; and
a third level above the second level, the third level comprising:
an electrode structure on the first conductive interconnect, the electrode structure comprising a first conductive hydrogen barrier layer and a first conductive fill material, wherein the electrode structure comprises a second lateral thickness;
an etch stop layer laterally surrounding the electrode structure;
a plurality of memory devices above the electrode structure, wherein individual ones of the plurality of memory devices comprises a perovskite material;
a plate electrode coupled between the plurality of memory devices and the electrode structure, wherein the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices;
an insulative hydrogen barrier layer encapsulating on at least a sidewall of the individual ones of the plurality of memory devices; and
a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices, and wherein the individual ones of the plurality of via electrodes comprise:
a second conductive hydrogen barrier layer comprising a lateral portion and substantially vertical portions connected to two ends of the lateral portion; and
a second conductive material on the lateral portion and between the substantially vertical portions;
a second region adjacent to the first region, the second region comprising:
a second conductive interconnect within the second level and wherein the third level further comprises:
a metal structure; and
a via structure coupled between the second conductive interconnect and the metal structure, wherein at least a sidewall of the via structure is adjacent to the etch stop layer.