US 12,439,605 B2
Semiconductor device, three-dimensional memory and method for fabricating the semiconductor device
Quan Zhang, Wuhan (CN); Lan Yao, Wuhan (CN); Jiaji Wu, Wuhan (CN); and Beibei Zhu, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Jul. 22, 2022, as Appl. No. 17/871,519.
Application 17/871,519 is a continuation of application No. PCT/CN2021/115851, filed on Sep. 10, 2021.
Prior Publication US 2023/0082694 A1, Mar. 16, 2023
Int. Cl. H10B 43/40 (2023.01); H10B 41/27 (2023.01); H10B 41/40 (2023.01); H10B 43/27 (2023.01)
CPC H10B 43/40 (2023.02) [H10B 41/27 (2023.02); H10B 41/40 (2023.02); H10B 43/27 (2023.02)] 17 Claims
OG exemplary drawing
 
1. A method for fabricating a semiconductor device, comprising:
forming a shallow trench isolation trench in a substrate, wherein the substrate comprises an active region, the shallow trench isolation trench is on a periphery of the active region, and the active region comprises a source region, a channel region, and a drain region;
forming a bottom isolating layer in a bottom portion of the shallow trench isolation trench;
forming a gate structure on the channel region, comprising:
forming a gate insulating layer on an inner surface of the shallow trench isolation trench and on the substrate;
forming a gate layer on the gate insulating layer; and
partially etching the gate insulating layer and the gate layer, such that remaining portions of the gate insulating layer and the gate layer on the channel region form the gate structure;
forming spacers having an ONO structure on sidewalls of the shallow trench isolation trench and sidewalls of the gate structure; and
forming a hard insulating layer in an upper portion of the shallow trench isolation trench and on sidewalls of the active region, such that the hard insulating layer covers the source region and the drain region.