US 12,439,604 B2
Semiconductor device and method of manufacturing the same
Kazuhiko Segi, Tokyo (JP); and Yoshiyuki Kawashima, Tokyo (JP)
Assigned to RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed by RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed on Apr. 20, 2023, as Appl. No. 18/303,909.
Claims priority of application No. 2022-097814 (JP), filed on Jun. 17, 2022.
Prior Publication US 2023/0413568 A1, Dec. 21, 2023
Int. Cl. H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/35 (2023.02) [H10B 43/40 (2023.02)] 15 Claims
OG exemplary drawing
 
1. A semiconductor device including a semiconductor element including a memory transistor and a select transistor, comprising:
a semiconductor substrate including a semiconductor-supporting substrate;
an element region defined in the semiconductor substrate, the element region including a first element region defined in the semiconductor-supporting substrate; and
the semiconductor element formed in the element region, the semiconductor element including the memory transistor and the select transistor that are electrically coupled in series, the memory transistor and the select transistor being formed in the first element region so as to be spaced apart from each other,
wherein the memory transistor has:
a memory-gate insulating film formed on a surface of the semiconductor-supporting substrate located in the first element region and including a charge storage layer;
a memory gate electrode formed on the memory-gate insulating film; and
a first impurity region including a first-impurity-region first portion and a first-impurity-region second portion,
wherein the select transistor has:
a select-gate insulating film formed on the surface of the semiconductor-supporting substrate located in the first element region;
a select gate electrode formed on the select-gate insulating film; and
a second impurity region including a second-impurity-region first portion and a second-impurity-region second portion,
wherein the first element region includes:
a first-element-region first portion defined in the semiconductor-supporting substrate located between the memory gate electrode and the select gate electrode;
a first-element-region second portion defined in the semiconductor-supporting substrate located at opposite side of the select gate electrode with respect to the memory gate electrode; and
a first-element-region third portion defined in the semiconductor-supporting substrate located at opposite side of the memory gate electrode with respect to the select gate electrode,
wherein, in the first-element-region second portion, a first raised portion is formed from the surface of the semiconductor-supporting substrate to a position higher than the surface,
wherein, in the first-element-region third portion, a second raised portion is formed from the surface of the semiconductor-supporting substrate to a position higher than the surface,
wherein, in the element region, a raised portion including the first raised portion and the second raised portion is formed,
wherein the raised portion is not formed in the first-element-region first portion, and each of the first-impurity-region first portion and the second-impurity-region first portion is formed in the first-element-region first portion in which the raised portion is not formed,
wherein the first-impurity-region second portion is formed in the first-element-region second portion so as to include the first raised portion,
wherein the second-impurity-region second portion is formed in the first-element-region third portion so as to include the second raised portion, and
wherein in each of the first-impurity-region first portion, the first-impurity-region second portion, the second-impurity-region first portion and the second-impurity-region second portion, an impurity concentration of a region close to a surface thereof is higher than an impurity concentration of a region far away from the surface thereof.