| CPC H10B 43/27 (2023.02) [H10B 43/10 (2023.02); H10B 43/35 (2023.02)] | 20 Claims |
|
1. A semiconductor device comprising:
a semiconductor substrate;
a peripheral circuit region on the semiconductor substrate;
a conductive layer on the peripheral circuit region;
a first polysilicon layer on the conductive layer;
a stack structure on the first polysilicon layer; and
a vertical structure penetrating through the stack structure and contacting at least one of the first polysilicon layer and the conductive layer,
wherein the stack structure includes a plurality of gate layers and a plurality of interlayer insulating layers alternately stacked on the first polysilicon layer,
wherein the vertical structure includes an insulating core region, a channel layer, and a plurality of data storage patterns,
wherein the insulating core region extends in a vertical direction, the vertical direction being perpendicular to an upper surface of the semiconductor substrate,
wherein the channel layer includes a first portion between the stack structure and the insulating core region and a second portion contacting the first polysilicon layer,
wherein the plurality of data storage patterns are between the channel layer and the plurality of gate layers in a horizontal direction parallel to the upper surface of the semiconductor substrate, and are spaced apart from each other in the vertical direction, and
wherein a lowermost data storage pattern among the plurality of data storage patterns is at a higher level than the first polysilicon layer.
|