US 12,439,601 B2
Semiconductor memory device and manufacturing method of the semiconductor memory device
Nam Jae Lee, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Dec. 13, 2022, as Appl. No. 18/080,472.
Application 18/080,472 is a continuation of application No. 17/074,062, filed on Oct. 19, 2020, granted, now 11,569,263.
Claims priority of application No. 10-2020-0058646 (KR), filed on May 15, 2020.
Prior Publication US 2023/0115446 A1, Apr. 13, 2023
Int. Cl. H10B 43/27 (2023.01); G11C 7/18 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/40 (2023.01); H10B 43/10 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/27 (2023.02) [G11C 7/18 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/40 (2023.02)] 15 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor memory device, the method comprising:
forming a first stack structure including interlayer insulating layers and sacrificial layers, which are alternately stacked;
forming a first conductive pattern overlapping the first stack structure;
forming a second conductive pattern overlapping with the first stack structure with the first conductive pattern interposed between the first stack structure and the second conductive pattern;
forming a hole penetrating the first stack structure, the first conductive pattern, and the second conductive pattern;
forming a multi-layer on a sidewall of the hole, wherein the multi-layer includes a first part extending along a sidewall of the first stack structure, a second part extending along a sidewall of the first conductive pattern, and a third part extending along a sidewall of the second conductive pattern, and a width of the second part is wider than that of each of the first part and the third part; and
forming a channel structure filling the hole on an inner wall of the multi-layer.