US 12,439,598 B2
Method of manufacturing semiconductor memory device and semiconductor memory device
Kyosuke Nanami, Yokkaichi Mie (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Sep. 1, 2022, as Appl. No. 17/901,642.
Claims priority of application No. 2022-044482 (JP), filed on Mar. 18, 2022.
Prior Publication US 2023/0301094 A1, Sep. 21, 2023
Int. Cl. H10B 43/27 (2023.01); H01L 21/311 (2006.01)
CPC H10B 43/27 (2023.02) [H01L 21/31144 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor memory device, comprising
forming a stacked body in which each of a plurality of first insulating layers and each of a plurality of second insulating layers are alternately stacked one on another;
forming a first mask layer above the stacked body, the first mask layer having a first side;
forming a first stopper layer, the first stopper layer covering at least the first side;
forming a second mask layer, the second mask layer covering the first mask layer having the first side;
repeating multiple times of a process of etching away one pair of first and second insulating layers of the stacked body exposed from the second mask layer, among the plurality of first and second insulating layers, with retracting the second mask layer in a first direction toward the first side by slimming;
removing the second mask layer undergone multiple times of the slimming, and removing the first stopper layer exposed on the first side; and
repeating multiple times of a process of etching away one pair of first and second insulating layers of the stacked body exposed from the first mask layer, among the plurality of first and second insulating layers, with retracting the first mask layer in the first direction by slimming.