US 12,439,597 B2
Three-dimensional semiconductor memory device and electronic system including the same
Yong-Hoon Son, Yongin-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 22, 2022, as Appl. No. 17/652,014.
Claims priority of application No. 10-2021-0070139 (KR), filed on May 31, 2021.
Prior Publication US 2022/0384478 A1, Dec. 1, 2022
Int. Cl. H10B 43/27 (2023.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional semiconductor memory device, comprising:
a substrate including a cell array region and a contact region extending from the cell array region;
a stack structure including interlayer dielectric layers and gate electrodes alternately and repeatedly stacked on the substrate;
a source structure between the substrate on the cell array region and the stack structure;
a mold structure between the substrate on the contact region and the stack structure; and
first vertical channel structures on the cell array region that are in vertical channel holes penetrating the stack structure and the source structure,
wherein each of the first vertical channel structures comprises a first barrier pattern, a data storage pattern, and a vertical semiconductor pattern, which are sequentially layered on an inner side surface of a corresponding one of the vertical channel holes,
wherein the mold structure comprises a first buffer insulating layer, a first semiconductor layer, a second buffer insulating layer, and a second semiconductor layer sequentially stacked on the substrate, and
wherein the source structure is in physical contact with a portion of a side surface of the vertical semiconductor pattern.