US 12,439,596 B2
Semiconductor memory device for suppressing variations of impurity concentrations
Takayuki Maruyama, Yokkaichi (JP); Yoshiaki Fukuzumi, Yokkaichi (JP); Yuki Sugiura, Yokkaichi (JP); Shinya Arai, Yokkaichi (JP); Fumie Kikushima, Yokkaichi (JP); Keisuke Suda, Yokkaichi (JP); and Takashi Ishida, Yokkaichi (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Dec. 22, 2021, as Appl. No. 17/559,786.
Application 17/559,786 is a continuation of application No. 16/296,276, filed on Mar. 8, 2019, abandoned.
Claims priority of application No. 2018-093926 (JP), filed on May 15, 2018.
Prior Publication US 2022/0115403 A1, Apr. 14, 2022
Int. Cl. H10B 43/27 (2023.01); H01L 21/768 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01); H01L 21/02 (2006.01)
CPC H10B 43/27 (2023.02) [H01L 21/76834 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H01L 21/02164 (2013.01); H01L 21/02238 (2013.01); H01L 21/02255 (2013.01); H01L 21/02271 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a first semiconductor layer;
a first insulating layer provided on the first semiconductor layer;
a plurality of electrode layers provided above the first insulating layer, the plurality of electrode layers stacked in a first direction;
a second semiconductor layer extending through the plurality of electrode layers and the first insulating layer in the first direction and extending inside the first semiconductor layer, the second semiconductor layer including a contact portion in contact with the first semiconductor layer; and
a first film provided inside the first semiconductor layer, wherein
the first semiconductor layer includes a first portion, a second portion, a third portion, a fourth portion, and a fifth portion, the first portion being provided in a position between the first film and the first insulating layer, the first film being provided in a position between the first portion and the second portion, the first and second portions being arranged in the first direction, the third portion being provided in a position between the first film and the second semiconductor layer, the third portion being connected to the first and second portions, the third portion of the first semiconductor layer being in contact with the contact portion of the second semiconductor layer, the fourth portion being located between the first film and the first portion in the first direction, the fifth portion being located between the first film and the second portion in the first direction,
the first film includes a first layer and a second layer, the first layer being provided between the second layer and the first semiconductor layer, the first layer being provided above, below, and to a side of the second layer, the second layer being comprised of a material different from a material of the first layer, and
a lower end of the first semiconductor layer is located lower than a lower end of the second semiconductor layer.