| CPC H10B 43/27 (2023.02) [H01L 23/5226 (2013.01); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H10D 62/292 (2025.01); H01L 24/32 (2013.01); H01L 25/0657 (2013.01); H01L 2224/32145 (2013.01)] | 19 Claims |
|
1. A semiconductor device, comprising:
a gate electrode structure on a substrate, the gate electrode structure including gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, each of the gate electrodes extending in a second direction parallel to the upper surface of the substrate;
a channel extending in the first direction through the gate electrode structure;
a division pattern at each of opposite sides of the gate electrode structure in a third direction, the third direction being parallel to the upper surface of the substrate and crossing the second direction, the division pattern extending in the second direction;
an insulation pattern structure extending through a portion of the gate electrode structure;
a through via extending in the first direction through the insulation pattern structure;
a first support structure extending in the first direction through the gate electrode structure; and
a second support structure extending in the first direction through a portion of the gate electrode structure between the insulation pattern structure and the division pattern,
wherein the second support structure includes:
a first extension portion extending in the second direction in a plan view; and
second extension portion connected to the first extension portion, the second extension portion extending in the third direction from the first extension portion,
wherein the second support structure has a shape of “C” or “U” in a plan view,
wherein the first support structure is one of a plurality of first support structures arranged in a support structure column extending in the second direction,
wherein the second support structure is one of a plurality of second support structures arranged as first and second support structure columns, which extend in the second direction while being spaced apart from each other in the third direction, and
wherein the first support structure column of the plurality of second support structures is arranged between the support structure column of the plurality of first support structures and the second support structure column of the plurality of second support structures.
|
|
14. A semiconductor device, comprising:
lower circuit patterns on a substrate, the substrate including a cell array region and an extension region at least partially surrounding the cell array region;
a common source plate (CSP) over the lower circuit patterns;
a gate electrode structure on the CSP, the gate electrode structure including gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, each of the gate electrodes extending in a second direction parallel to the upper surface of the substrate;
a memory channel structure extending through the gate electrode structure on the cell array region and contacting an upper surface of the CSP, the memory channel structure including:
a channel extending in the first direction; and
a charge storage structure on an outer sidewall of the channel;
a division pattern at each of opposite sides of the gate electrode structure in a third direction, the third direction being parallel to the upper surface of the substrate and crossing the second direction, the division pattern extending in the second direction;
an insulation pattern structure extending through a portion of the gate electrode structure on the CSP;
a through via extending in the first direction through the insulation pattern structure and the CSP, the through via contacting one of the lower circuit patterns and electrically connected thereto;
a contact plug extending in the first direction to contact an upper surface of an end portion in the second direction of one of the gate electrodes;
a first support structure extending in the first direction through the gate electrode structure and contacting an upper surface of the CSP, the first support structure being adjacent to the contact plug; and
a second support structure extending in the first direction through a portion of the gate electrode structure between the insulation pattern structure and the division pattern, and contacting an upper surface of the CSP,
wherein the second support structure has a shape of “C” or “U” in a plan view,
wherein the first structure is one of a plurality of first support structures arranged in a support structure column extending in the second direction,
wherein the second support structure is one of a plurality of second support structures arranged as first and second support structure columns, which extend in the second direction while being spaced apart from each other in the third direction, and
wherein the first support structure column of the plurality of second support structures is arranged between the support structure column of the plurality first support structures and the second support structure column of the plurality of second support structures.
|
|
18. A massive data storage system, comprising:
a semiconductor device having:
a memory cell structure including:
a gate electrode structure on a substrate, the gate electrode structure including gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, each of the gate electrodes extending in a second direction parallel to the upper surface of the substrate;
a channel extending in the first direction through the gate electrode structure;
a division pattern at each of opposite sides of the gate electrode structure in a third direction, the third direction being parallel to the upper surface of the substrate and crossing the second direction, the division pattern extending in the second direction;
an insulation pattern structure extending through a portion of the gate electrode structure;
a through via extending in the first direction through the insulation pattern structure;
a first support structure extending in the first direction through the gate electrode structure; and
a second support structure extending in the first direction through a portion of the gate electrode structure between the insulation pattern structure and the division pattern, the second support structure including a first extension portion extending in the second direction in a plan view, and including a second extension portion connected to the first extension portion, the second extension portion extending in the third direction from the first extension portion;
peripheral circuit wirings configured to apply electrical signals to the memory cell structure; and
an input/output pad electrically connected to the peripheral circuit wirings; and
a controller electrically connected to the semiconductor device through the input/output pad, the controller configured to control the semiconductor device,
wherein the second support structure has a shape of “C” or “U” in a plan view,
wherein the first support structure is one of a plurality of first support structures arranged in a support structure column extending in the second direction,
wherein the second support structure is one of a plurality of second support structures arranged as first and second support structure columns, which extend in the second direction while being spaced apart from each other in the third direction, and
wherein the first support structure column of the plurality of second support structures is arranged between the support structure column of the plurality of first support structures and the second support structure column of the plurality of second support structures.
|