US 12,439,594 B2
Semiconductor device and manufacturing method thereof
Wei-Cheng Wu, Zhubei (TW); and Li-Feng Teng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 5, 2024, as Appl. No. 18/764,868.
Application 18/764,868 is a continuation of application No. 18/231,427, filed on Aug. 8, 2023, granted, now 12,058,856.
Application 18/231,427 is a continuation of application No. 17/135,744, filed on Dec. 28, 2020, granted, now 11,825,651, issued on Nov. 21, 2023.
Application 17/135,744 is a continuation of application No. 16/427,733, filed on May 31, 2019, granted, now 10,879,253, issued on Dec. 29, 2020.
Application 16/427,733 is a continuation of application No. 15/428,823, filed on Feb. 9, 2017, granted, now 10,325,918, issued on Jun. 18, 2019.
Claims priority of provisional application 62/427,389, filed on Nov. 29, 2016.
Prior Publication US 2024/0365542 A1, Oct. 31, 2024
Int. Cl. H10B 41/42 (2023.01); H10B 41/30 (2023.01); H10B 41/35 (2023.01); H10B 41/44 (2023.01); H10B 41/47 (2023.01); H10B 41/48 (2023.01); H10B 43/30 (2023.01); H10D 30/68 (2025.01); H10D 30/69 (2025.01); H10D 64/01 (2025.01)
CPC H10B 41/42 (2023.02) [H10B 41/30 (2023.02); H10B 41/35 (2023.02); H10B 41/44 (2023.02); H10B 41/47 (2023.02); H10B 41/48 (2023.02); H10B 43/30 (2023.02); H10D 30/6892 (2025.01); H10D 30/696 (2025.01); H10D 64/017 (2025.01); H10D 64/035 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device including a non-volatile memory, the non-volatile memory comprising:
a first dielectric layer disposed on a substrate comprising a stepped surface;
a floating gate disposed on the first dielectric layer;
a control gate;
a select gate;
an erase gate; and
a second dielectric layer disposed between the floating gate and the control gate, and having one of a silicon nitride layer, a silicon oxide layer, and a multi-layer thereof, wherein the first dielectric layer includes silicon oxide,
wherein the first dielectric layer comprises a multi-layer structure including at least a first layer that extends below the select gate, and a second layer that does not extend below the select gate.