| CPC H10B 41/27 (2023.02) [H10B 41/20 (2023.02); H10B 43/20 (2023.02); H10B 43/27 (2023.02); H10B 41/00 (2023.02); H10B 43/00 (2023.02)] | 12 Claims |

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1. A semiconductor memory device comprising:
a substrate;
a plurality of first conductive layers and a plurality of first insulating layers alternately arranged in a first direction, the first direction intersecting the substrate;
a first semiconductor layer extending in the first direction, the first semiconductor layer facing the first conductive layers and the first insulating layers;
a charge storage layer disposed between the first conductive layers and the first semiconductor layer; and
a second semiconductor layer connected to one end of the first semiconductor layer in the first direction, wherein
the second semiconductor layer contains a first element,
the first element is at least one of phosphorus (P), arsenic (As), carbon (C), or argon (Ar),
the second semiconductor layer including:
a fourth region,
a fifth region disposed between the fourth region and the charge storage layer,
a sixth region disposed above the fourth region,
a seventh region disposed between the sixth region and the charge storage layer, and
an eighth region disposed between the fifth region and the seventh region, and directly contacting the first semiconductor layer,
wherein a concentration of the first element in the fifth region is larger than a concentration of the first element in the fourth region, and a concentration of the first element in seventh region is larger than a concentration of the first element in the sixth region and fourth region.
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