US 12,439,591 B2
Memory device, integrated circuit and manufacturing method of the same
Te-Hsun Hsu, Hsinchu County (TW)
Assigned to Ipcell Corporation Limited, Hong Kong (HK)
Filed by Ipcell Corporation Limited, Hong Kong (HK)
Filed on Jan. 4, 2024, as Appl. No. 18/403,730.
Claims priority of application No. 202310436039.7 (CN), filed on Apr. 21, 2023.
Prior Publication US 2024/0357805 A1, Oct. 24, 2024
Int. Cl. G11C 17/00 (2006.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01); H10B 20/25 (2023.01)
CPC H10B 20/25 (2023.02) [G11C 17/16 (2013.01); G11C 17/18 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising a one-time programmable non-volatile memory cell that comprises:
a first transistor, a control terminal of the first transistor and a first terminal of the first transistor coupled to a write word line and a source line respectively;
a second transistor that has a control terminal coupled to a second terminal of the first transistor and has a first terminal coupled to a bit line;
a fuse element, wherein a first terminal of the fuse element is coupled to the second terminal of the first transistor and the control terminal of the second transistor; and
a third transistor, wherein a control terminal of the third transistor is coupled to a read word line, a first terminal of the third transistor is coupled to the source line and a second terminal of the third transistor is coupled to a second terminal of the second transistor,
wherein the first transistor is configured to be turned on to form a write path to the fuse element, and the second transistor and the third transistor are configured as a read path.