US 12,439,590 B2
Memory device
Guobiao Zhang, Corvallis, OR (US); and Zhitang Song, ShangHai (CN)
Assigned to Southern University of Science and Technology, GuangDong (CN)
Filed by Guobiao Zhang, Corvallis, OR (US); and Zhitang Song, ShangHai (CN)
Filed on Aug. 4, 2022, as Appl. No. 17/881,597.
Claims priority of application No. 202110903910.0 (CN), filed on Aug. 6, 2021; application No. 202111641964.0 (CN), filed on Dec. 29, 2021; application No. 202210691159.7 (CN), filed on Jun. 17, 2022; and application No. 202210871271.9 (CN), filed on Jul. 22, 2022.
Prior Publication US 2023/0044721 A1, Feb. 9, 2023
Int. Cl. H10B 20/25 (2023.01)
CPC H10B 20/25 (2023.02) 11 Claims
OG exemplary drawing
 
1. A three-dimensional memory, comprising:
a semiconductor substrate;
a plurality of first and second address lines above said semiconductor substrate, wherein said first and second address lines intersect each other; and,
a plurality of one-time-programmable memory (OTP) devices disposed at the intersections between said first and second address lines;
each of said devices comprising a memory layer between said first and second address lines, wherein said memory layer comprises at least an OTS film, and the total thickness of said memory layer is smaller than or equal to 60 nm.