US 12,439,588 B2
Method of forming a memory cell with a transistor and a capacitor
Chao-Chun Lu, Taipei (TW)
Assigned to Etron Technology, Inc., Hsinchu (TW); and Invention And Collaboration Laboratory Pte. Ltd., Singapore (SG)
Filed by Etron Technology, Inc., Hsinchu (TW); and Invention And Collaboration Laboratory Pte. Ltd., Singapore (SG)
Filed on Sep. 18, 2023, as Appl. No. 18/369,213.
Application 18/369,213 is a continuation of application No. 17/337,391, filed on Jun. 2, 2021, granted, now 11,825,645.
Claims priority of provisional application 63/034,411, filed on Jun. 4, 2020.
Prior Publication US 2024/0008256 A1, Jan. 4, 2024
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/315 (2023.02) [H10B 12/0335 (2023.02); H10B 12/053 (2023.02); H10B 12/34 (2023.02); H10B 12/482 (2023.02)] 8 Claims
OG exemplary drawing
 
1. A method of forming a memory cell with a transistor and a capacitor, comprising:
preparing a semiconductor substrate with an semiconductor surface;
forming the transistor coupled to the semiconductor surface, the transistor comprising a gate structure, a first conductive region, and a second conductive region;
selective growing a storage electrode of the capacitor by epitaxy, wherein the storage electrode covers two sides and all top surface of the gate structure of the transistor and electrically coupled to the second conductive region of the transistor; and
forming a dielectric layer of the capacitor and a counter electrode of the capacitor over the storage electrode.