US 12,439,585 B2
Semiconductor device and manufacturing method of semiconductor device
Jae Hyun Han, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jun. 17, 2022, as Appl. No. 17/843,921.
Application 17/843,921 is a continuation of application No. 17/158,935, filed on Jan. 26, 2021, granted, now 11,393,823.
Claims priority of application No. 10-2020-0097001 (KR), filed on Aug. 3, 2020.
Prior Publication US 2022/0328490 A1, Oct. 13, 2022
Int. Cl. H10B 12/00 (2023.01); H10D 30/63 (2025.01); H10D 64/27 (2025.01)
CPC H10B 12/31 (2023.02) [H10B 12/33 (2023.02); H10D 30/63 (2025.01); H10D 64/512 (2025.01)] 11 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
forming a first array including a first bit line extending in a first direction, a first word line extending in a second direction intersecting the first direction, and a first transistor being located at a first intersection of the first word line and the first bit line, the first transistor being connected to the first word line and the first bit line;
forming a first capacitor electrically connected to the first transistor, the first capacitor being located at a first part of the first intersection; and
forming a second capacitor located at a second part of the first intersection,
wherein forming of the first capacitor and forming of the second capacitor include:
forming first electrode layers of the first and second capacitors extending in a vertical direction and overlapping with the first intersection in the vertical direction;
forming a dielectric layer surrounding each of sidewalls of the first electrode layers; and
forming a second electrode layer surrounding the sidewall of the first electrode layer of the first capacitor and continuously extending to surround the sidewall of the first electrode layer of the second capacitor, wherein the dielectric layer is disposed between the second electrode and each of the first electrode layers.