| CPC H10B 12/20 (2023.02) | 10 Claims |

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1. A three-dimensional memory device comprising:
a memory cell comprising:
a pillar;
an insulating layer surrounding the pillar;
a first gate contact surrounding a first portion of the insulating layer, the first gate contact coupled to a word line configured to address and non-destructively read the pillar;
a second gate contact surrounding a second portion of the insulating layer, the second gate contact coupled to a plate line configured to program the pillar; and
an annular dielectric layer radially separating the pillar into a channel and a body, the body to store an electrical charge, the annular dielectric layer between the body of the pillar and the insulating layer.
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