US 12,439,583 B2
Semiconductor structure manufacturing method and semiconductor structure
Daohuan Feng, Hefei (CN); and Xiaojie Li, Hefei (CN)
Assigned to Changxin Memory Technologies, Inc., Hefei (CN)
Filed by Changxin Memory Technologies, Inc., Anhui (CN)
Filed on Jan. 6, 2023, as Appl. No. 18/093,969.
Application 18/093,969 is a continuation of application No. PCT/CN2022/108097, filed on Jul. 27, 2022.
Claims priority of application No. 202210663531.3 (CN), filed on Jun. 13, 2022.
Prior Publication US 2023/0403841 A1, Dec. 14, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/056 (2023.02) 17 Claims
OG exemplary drawing
 
1. A semiconductor structure manufacturing method, comprising:
providing a substrate and forming a groove in the substrate;
forming a barrier layer on a sidewall of the groove;
epitaxially growing a channel material from a bottom of the groove to form an intermediate structure in the groove; and
removing a portion of the intermediate structure and a portion of the substrate to form a fin structure;
wherein the forming the groove in the substrate includes:
forming a first sacrificial layer on the substrate, and etching the first sacrificial layer to form a first opening; and
etching a portion of the substrate along the first opening to form the groove;
and wherein the first sacrificial layer includes a third insulating layer, a fourth insulating layer, and a fifth insulating layer, the third insulating layer covers a surface of the substrate, the fourth insulating layer is located between the third insulating layer and the fifth insulating layer, and the fifth insulating layer covers a side of the fourth insulating layer that is away from the substrate.