US 12,439,582 B2
Deep trench capacitor and method for forming the same
Ming-Hsun Lin, Hsinchu (TW); and Jyun-Ying Lin, Yilan County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Feb. 23, 2023, as Appl. No. 18/173,489.
Claims priority of provisional application 63/381,412, filed on Oct. 28, 2022.
Prior Publication US 2024/0147689 A1, May 2, 2024
Int. Cl. H10B 12/00 (2023.01); H10D 1/00 (2025.01); H10D 1/66 (2025.01)
CPC H10B 12/0387 (2023.02) [H10D 1/047 (2025.01); H10D 1/665 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC), comprising:
a charge-storing device comprising:
a first charge-storing stack extending into a substrate; and
a second charge-storing stack extending into the substrate and adjacent to the first charge-storing stack along a first direction,
wherein:
the first charge-storing stack and the second charge-storing stack comprise:
a liner layer over the substrate; and
a plurality of dielectric layers and a plurality of conductive layers over the liner layer in an alternating manner;
the first charge-storing stack and the second charge-storing stack extend lengthwise along a second direction perpendicular to the first direction;
the first charge-storing stack has a length along the second direction;
a spacing between the first charge-storing stack and the second charge-storing stack is no more than about 10% of the length along the first direction;
the first charge-storing stack and the second charge-storing stack have an offset along the second direction; and
the offset is between about ⅓ of the length and about ⅔ of the length.