US 12,439,580 B2
Semiconductor memory cell structure, semiconductor memory, preparation method and application thereof
Qi Wang, Beijing (CN); and Huilong Zhu, Beijing (CN)
Assigned to BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY, Beijing (CN); and INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES, Beijing (CN)
Appl. No. 17/770,856
Filed by Beijing Superstring Academy of Memory Technology, Beijing (CN); and INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES, Beijing (CN)
PCT Filed Dec. 9, 2021, PCT No. PCT/CN2021/136853
§ 371(c)(1), (2) Date Jun. 8, 2023,
PCT Pub. No. WO2023/097743, PCT Pub. Date Jun. 8, 2023.
Claims priority of application No. 202111456087.X (CN), filed on Dec. 1, 2021.
Prior Publication US 2024/0147686 A1, May 2, 2024
Int. Cl. H10B 12/00 (2023.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01)
CPC H10B 12/00 (2023.02) [H10D 30/0321 (2025.01); H10D 30/6733 (2025.01); H10D 30/6755 (2025.01); H10D 30/6757 (2025.01)] 23 Claims
OG exemplary drawing
 
1. A semiconductor memory cell structure comprising:
a substrate; and
a first transistor layer, an isolation layer and a second transistor layer that are vertically stacked on the substrate from bottom to top;
wherein:
the first transistor layer comprises: a first stack structure formed by stacking a first source, a first channel and a first drain from bottom to top; and a first gate located on a sidewall of the first stack structure; wherein the first gate and the sidewall of the first stack structure are isolated by a gate dielectric layer, and the first gate and the substrate are isolated by the gate dielectric layer; and
the second transistor layer comprises: a second stack structure formed by stacking a second drain, a second channel and a second source from bottom to top; and a second gate located on a sidewall of the second stack structure; wherein the second gate and the sidewall of the second stack structure are isolated by the gate dielectric layer, at least a part of a sidewall of the second drain is in direct contact with the first gate, and the first gate and the second gate are isolated by a dielectric material in a vertical direction.