US 12,439,528 B2
Method of preparing a high density interconnect printed circuit board including microvias filled with copper
Bert Reents, Berlin (DE); Akif Özkök, Berlin (DE); Soungsoo Kim, Berlin (DE); Horst Brüggmann, Berlin (DE); Herwig Josef Berthold, Berlin (DE); Marcin Klobus, Berlin (DE); Thomas Schiwon, Berlin (DE); and Marko Mirkovic, Berlin (DE)
Assigned to Atotech Deutschland Gmbh & Co. KG, Berlin (DE)
Filed by Atotech Deutschland GmbH & Co. KG, Berlin (DE)
Filed on Jun. 18, 2024, as Appl. No. 18/746,837.
Application 18/746,837 is a continuation of application No. 17/636,502, granted, now 12,245,383, previously published as PCT/EP2020/073186, filed on Aug. 19, 2020.
Claims priority of application No. 19192196 (EP), filed on Aug. 19, 2019.
Prior Publication US 2024/0341042 A1, Oct. 10, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H05K 3/42 (2006.01); C25D 3/38 (2006.01); C25D 5/02 (2006.01); C25D 5/18 (2006.01); C25D 5/34 (2006.01); C25D 5/48 (2006.01); C25D 7/00 (2006.01); H01L 21/48 (2006.01); H01L 21/768 (2006.01); H05K 3/10 (2006.01); H05K 3/46 (2006.01); H05K 3/18 (2006.01)
CPC H05K 3/425 (2013.01) [C25D 3/38 (2013.01); C25D 5/022 (2013.01); C25D 5/18 (2013.01); C25D 5/34 (2013.01); C25D 5/48 (2013.01); C25D 7/00 (2013.01); H01L 21/4857 (2013.01); H01L 21/76877 (2013.01); H05K 3/108 (2013.01); H05K 3/423 (2013.01); H05K 3/429 (2013.01); H05K 3/4623 (2013.01); H05K 3/181 (2013.01); H05K 2203/0353 (2013.01); H05K 2203/072 (2013.01); H05K 2203/0723 (2013.01); H05K 2203/1492 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A method of preparing a high density interconnect printed circuit board (HDI PCB) including microvias filled with copper, the method comprising the steps of:
a2) providing a multi-layer substrate (10) comprising
(i) a stack assembly of an electrically conductive interlayer (14) embedded between two insulating layers (12) having a peripheral surface,
(ii) a microvia (20) extending from the peripheral surface of the insulating layers (12) of the multi-layer substrate (10) and ending on the conductive interlayer (14);
b2) depositing a conductive layer (30) on the peripheral surface of the insulating layers (12) of the multi-layer substrate (10) and on an inner surface of the microvia (20);
c) electrodepositing a copper filling (42) in the microvia (20) and a first copper layer (40) on the conductive layer (30) wherein a thickness of the first copper layer (40) is from 0.1 to 3 μm and wherein the copper filling (42) and the first copper layer (40) form together a planar surface (32);
and, subsequent to step c):
d) forming a patterned masking film (50) on the first copper layer (40);
e) electrodepositing a second copper layer (60) in the area not covered by the patterned masking film (50); and
f) removing the patterned masking film (50).