US 12,439,289 B2
Signalling support for redundancy capabilities for EHT
Necati Canpolat, Beaverton, OR (US); Juan Fang, Portland, OR (US); Ganesh Venkatesan, Hillsboro, OR (US); Chittabrata Ghosh, Fremont, CA (US); and Dave A. Cavalcanti, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 17/925,129
Filed by Intel Corporation, Santa Clara, CA (US)
PCT Filed Jul. 23, 2021, PCT No. PCT/US2021/042896
§ 371(c)(1), (2) Date Nov. 14, 2022,
PCT Pub. No. WO2022/020677, PCT Pub. Date Jan. 27, 2022.
Claims priority of provisional application 63/133,645, filed on Jan. 4, 2021.
Claims priority of provisional application 63/056,019, filed on Jul. 24, 2020.
Prior Publication US 2023/0199546 A1, Jun. 22, 2023
Int. Cl. H04W 28/02 (2009.01); H04L 1/08 (2006.01); H04W 8/24 (2009.01)
CPC H04W 28/0231 (2013.01) [H04L 1/08 (2013.01); H04W 8/24 (2013.01); H04W 28/0215 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus of an extremely high-throughput (EHT) station (STA), the apparatus comprising: processing circuitry and memory, wherein the processing circuitry is configured to:
encode a management frame for transmission, the management frame encoded to include a quality-of-service (QoS) capability element that includes a QoS information field configured to signal QoS redundancy capability;
set a QoS redundancy bit in the QoS information field of the QoS capabilities element to indicate that the EHT STA supports redundancy for QoS data frames; and
generate an Extended Capabilities element to include in the management frame and set a redundancy indicator bit in the Extended Capabilities element to indicate that the EHT STA supports redundancy for a subset of management frames.