US 12,439,184 B2
Image sensor including time-division controlled correlated double sampler and electronic device including the same
Seokyong Park, Suwon-si (KR); Kyungmin Kim, Suwon-si (KR); and Donghyun Kim, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-Do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 6, 2023, as Appl. No. 18/329,836.
Claims priority of application No. 10-2022-0087798 (KR), filed on Jul. 15, 2022; and application No. 10-2023-0020816 (KR), filed on Feb. 16, 2023.
Prior Publication US 2024/0022800 A1, Jan. 18, 2024
Int. Cl. H04N 25/78 (2023.01); H04N 25/585 (2023.01); H04N 25/59 (2023.01); H04N 25/616 (2023.01); H04N 25/778 (2023.01)
CPC H04N 25/78 (2023.01) [H04N 25/585 (2023.01); H04N 25/59 (2023.01); H04N 25/616 (2023.01); H04N 25/778 (2023.01)] 18 Claims
OG exemplary drawing
 
1. An image sensor comprising:
a pixel array including a first pixel connected to a first column line and a second pixel connected to a second column line, each of the first pixel and the second pixel including a first photodiode (PD) and a second PD, which share a driving transistor, the first and second pixels configured to operate in a first mode and a second mode according to a conversion gain based on the respective first PD, and the first and second pixels configured to operate in a third mode and a fourth mode based on the respective second PD; and
an analog-to-digital converter including a first correlated double sampling (CDS) circuit, a second CDS circuit, and a third CDS circuit, which are configured to read pixel signals output through the first column line and the second column line,
wherein the first CDS circuit is configured to connect to the first column line and the second column line in a time-division manner,
wherein the first CDS circuit is configured to read, in a first period, a first mode pixel signal of the first pixel that is output through the first column line, and is configured to read, in a second period after the first period, a first mode pixel signal of the second pixel that is output through the second column line, and
wherein the second CDS circuit is configured to read, in the first period, a second mode pixel signal of the first pixel that is output through the first column line, and is configured to read, in the second period, a second mode pixel signal of the second pixel that is output through the second column line.