US 12,439,172 B2
Auxiliary engine for hardware virtualization
Abhijeet Dey, Bengaluru (IN); Animesh Behera, Bengaluru (IN); Joby Abraham, Bangalore (IN); and Amrit Anand Amresh, Bangalore (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Nov. 29, 2022, as Appl. No. 18/059,856.
Prior Publication US 2024/0179422 A1, May 30, 2024
Int. Cl. H04N 23/80 (2023.01)
CPC H04N 23/80 (2023.01) 17 Claims
OG exemplary drawing
 
1. An apparatus for processing data, the apparatus comprising:
an auxiliary processing engine; and
two or more symmetrical processing engines coupled to the auxiliary processing engine, each symmetrical processing engine of the two or more symmetrical processing engines including a pipeline of processing modules, wherein the two or more symmetrical processing engines and the auxiliary processing engine are configured to preprocess image data for an image signal processor, wherein the auxiliary processing engine is configured to receive output data from one of the two or more symmetrical processing engines at a time, and to switch between receiving output data from the symmetrical processing engine to an additional symmetrical processing engine of the two or more symmetrical processing engines, and wherein a symmetrical processing engine of the two or more symmetrical processing engines is configured to:
receive input data, wherein any one of the two or more symmetrical processing engines is configured to receive the input data from any of a plurality of image sensors;
receive an indication to process the input data using a module of the auxiliary processing engine;
transmit output data to the auxiliary processing engine;
receive processed data from the auxiliary processing engine;
further process the processed data in one or more portions of a pipeline of modules of the symmetrical processing engine to generate further processed data; and
output the further processed data for processing by the image signal processor.