US 12,439,138 B2
Semiconductor device and imaging device
Wataru Saito, Tokyo (JP); and Fukashi Morishita, Tokyo (JP)
Assigned to Renesas Electronics Corporation, Tokyo (JP)
Filed by Renesas Electronics Corporation, Tokyo (JP)
Filed on Oct. 31, 2023, as Appl. No. 18/498,278.
Claims priority of application No. 2022-184942 (JP), filed on Nov. 18, 2022.
Prior Publication US 2024/0171835 A1, May 23, 2024
Int. Cl. H04N 23/52 (2023.01); H04N 23/68 (2023.01)
CPC H04N 23/52 (2023.01) [H04N 23/6812 (2023.01); H04N 23/687 (2023.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor device comprising a first programmable gain amplifier,
wherein the first programmable gain amplifier includes:
a positive input node and a negative input node to which differential input voltages having an offset voltage are input;
a fully differential amplifier;
a first node to which a first correction voltage is input;
a second node to which a second correction voltage is input;
a first resistance element connected between the positive input node and a non-inverting input node of the fully differential amplifier;
a second resistance element connected between the negative input node and an inverting input node of the fully differential amplifier;
a third resistance element connected between the non-inverting input node and an inverting output node of the fully differential amplifier;
a fourth resistance element connected between the inverting input node and a non-inverting output node of the fully differential amplifier;
a fifth resistance element connected between the non-inverting input node of the fully differential amplifier and the first node; and
a sixth resistance element connected between the inverting input node of the fully differential amplifier and the second node.