US 12,439,102 B2
Trick mode operation with multiple video streams
Jason W. Herrick, San Jose, CA (US); Daniel William English, Andover, MA (US); and Wade K. Wan, Irvine, CA (US)
Assigned to Avago Technologies International Sales Pte. Limited, Singapore (SG)
Filed by Avago Technologies International Sales Pte. Limited, Singapore (SG)
Filed on May 27, 2022, as Appl. No. 17/826,862.
Application 17/826,862 is a division of application No. 16/265,870, filed on Feb. 1, 2019, granted, now 11,350,140.
Application 16/265,870 is a continuation of application No. 15/050,120, filed on Feb. 22, 2016, granted, now 10,205,975, issued on Feb. 12, 2019.
Claims priority of provisional application 62/281,094, filed on Jan. 20, 2016.
Prior Publication US 2022/0295125 A1, Sep. 15, 2022
Int. Cl. H04N 21/234 (2011.01); H04N 21/2343 (2011.01); H04N 21/2387 (2011.01); H04N 21/462 (2011.01); H04N 21/472 (2011.01)
CPC H04N 21/23424 (2013.01) [H04N 21/23439 (2013.01); H04N 21/2387 (2013.01); H04N 21/4621 (2013.01); H04N 21/47217 (2013.01)] 26 Claims
OG exemplary drawing
 
1. A system, comprising:
a circuit configured to:
decode a first video stream at a first rate simultaneously with decoding a second video stream at a second rate different from the first rate;
one or more frame buffers configured to store decoded video frames generated from the circuit;
a processor configured to:
determine that decoding the first video stream at the first rate consumes more decoding power or decoding performance than decoding the second video stream at the second rate; and
in response to the determination, decode the second video stream at the second rate while stopping decoding of the first video stream,
wherein a display engine is configured to select decoded video frames of the second video stream from the one or more frame buffers for display via a connection to a client device.