| CPC H04N 19/40 (2014.11) [H04N 19/105 (2014.11); H04N 19/149 (2014.11); H04N 19/172 (2014.11)] | 22 Claims |

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1. A device comprising:
one or more processors; and
memory storing instructions that, when executed by the one or more processors, cause the device to:
receive data associated with a first plurality of frames encoded by one or more transcoders, wherein the data indicates, for each frame of the first plurality of frames, a frame type and timing information;
determine, based on the data and during encoding of a second plurality of frames, a degree of similarity between the first plurality of frames and the second plurality of frames, wherein the degree of similarity indicates one or more matching content features;
synchronize, based on the one or more matching content features and the timing information, the second plurality of frames with the first plurality of frames; and
encode, based on the synchronizing, the second plurality of frames to contain the timing information.
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