US 12,439,062 B2
Encoder, decoder, encoding method, and decoding method
Takahiro Nishi, Nara (JP); Tadamasa Toma, Osaka (JP); and Kiyofumi Abe, Osaka (JP)
Assigned to PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA, Torrance, CA (US)
Filed by Panasonic Intellectual Property Corporation of America, Torrance, CA (US)
Filed on Jun. 15, 2022, as Appl. No. 17/841,191.
Application 17/841,191 is a continuation of application No. PCT/JP2021/004850, filed on Feb. 9, 2021.
Claims priority of provisional application 62/972,254, filed on Feb. 10, 2020.
Prior Publication US 2022/0312023 A1, Sep. 29, 2022
Int. Cl. H04N 19/169 (2014.01); H04N 19/30 (2014.01); H04N 19/70 (2014.01)
CPC H04N 19/188 (2014.11) [H04N 19/30 (2014.11); H04N 19/70 (2014.11)] 8 Claims
OG exemplary drawing
 
1. An encoder comprising:
circuitry; and
memory coupled to the circuitry, wherein in operation, the circuitry:
determines whether a total number of one or more PTL parameters is equal to a total number of one or more layer groups, the one or more PTL parameters each indicating information including profile information, level information, and tier information, the one or more layer groups each including at least one output layer; and
when the total number of the one or more PTL parameters is equal to the total number of the one or more layer groups,
(i) determines, using a determined method, a correspondence relationship for associating any of the one or more PTL parameters with each of the one or more layer groups, and
(ii) omits storing information indicating the correspondence relationship in a common header shared between layers in the one or more layer groups.