| CPC H04N 19/105 (2014.11) [H04N 19/119 (2014.11); H04N 19/139 (2014.11); H04N 19/14 (2014.11); H04N 19/176 (2014.11); H04N 19/52 (2014.11); H04N 19/573 (2014.11)] | 4 Claims |

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1. A decoder comprising:
circuitry; and
memory,
wherein, using the memory, the circuitry:
in a first operating mode,
derives first motion vectors for a first block obtained by splitting a picture, using a first inter prediction scheme, and
generates a prediction image corresponding to the first block, by referring to spatial gradients of luminance generated based on the first motion vectors; and
in a second operating mode,
derives second motion vectors for a sub-block obtained by splitting a second block, using a second inter prediction scheme different from the first inter prediction scheme, the second block being obtained by splitting the picture, and
generates a prediction image corresponding to the sub-block without referring to spatial gradients of luminance.
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