US 12,438,959 B2
High-speed data packet generator
Aaron Foo, Tokyo (JP)
Assigned to Fmad Engineering (SNG) Pte Ltd., Singapore (SG)
Filed by fmad engineering kabushiki gaisha, Tokyo (JP)
Filed on Aug. 19, 2021, as Appl. No. 17/406,385.
Application 17/406,385 is a continuation of application No. 16/590,855, filed on Oct. 2, 2019, granted, now 11,128,740.
Application 16/590,855 is a continuation in part of application No. 16/528,952, filed on Aug. 1, 2019, granted, now 10,831,408, issued on Nov. 10, 2020.
Application 16/528,952 is a continuation of application No. 15/609,729, filed on May 31, 2017, granted, now 10,423,358, issued on Sep. 24, 2019.
Prior Publication US 2021/0385308 A1, Dec. 9, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 69/22 (2022.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 11/10 (2006.01); H04L 69/324 (2022.01); H04L 69/16 (2022.01)
CPC H04L 69/22 (2013.01) [G06F 9/30098 (2013.01); G06F 9/3853 (2013.01); G06F 11/1004 (2013.01); H04L 69/324 (2013.01); H04L 69/16 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A system comprising:
a plurality of registers;
instruction memory; and
an execution unit configured to generate a sequence of outputs by executing a set of instructions stored in the instruction memory on values stored in the plurality of registers, wherein executing an instruction from the set of instructions involves: reading one or more of the values from the plurality of registers; generating a data payload based on the one or more of the values; and appending at least four control bits from the instruction to the data payload, wherein the control bits define how the data payload is to be placed in a data packet, and wherein the control bits define a count of valid bytes in the data payload and a number of times that the execution unit is to repeatedly execute the instruction; and
a processor configured to generate, from the sequence of outputs, the data packet.